US Patent 10529624 Simple contact over gate on active area

Semiconductor devices and methods are provided to fabricate FET devices having overlapping gate and source/drain contacts while preventing electrical shorts between the overlapping gate and source/drain contacts. For example, a semiconductor device includes a plurality of semiconductor fins patterned in a starting semiconductor substrate; a set of gate structures formed on the starting semiconductor substrate; a set of spacers formed around each of the set of gate structures; a source and drain region grown around the plurality of fins; a conductive metal material on the source and drain region, an insulating material is configured to be deposited over an upper surface of the conductive metal material and the gate structure; and a plurality of contacts in the insulator material. The plurality of contacts is formed such that a bottom surface of the plurality of contacts is in contact with at least a portion of the upper surface of the gate structure. The plurality of contacts is further formed such that the plurality of contacts are positioned in at least a portion of the insulating material configured to be deposited over the upper surface of the conductive metal material.