US Patent 12107147 Self-aligned gate contact for VTFETs

Semiconductor devices and methods of forming the same include forming dummy gate spacers in a trench in a semiconductor substrate. A dummy gate is formed in the trench. An exposed dummy gate spacer is replaced with a sacrificial spacer. A cap layer is formed over the dummy gate. The cap layer is etched to expose the dummy gate. The sacrificial spacer is replaced with an isolation dielectric spacer. The dummy gate is replaced with a conductor.