US Patent 10546772 Self-aligned via below subtractively patterned interconnect
Patent 10546772 was granted and assigned to Intel on January, 2020 by the United States Patent and Trademark Office.
All edits
Edits on 22 Feb, 2024
Golden AI
Edits made to:
Infobox (+1 properties)
Infobox
Patent Citations Received
Edits on 11 Dec, 2023
Golden AI
Edits made to:
Article (+279 characters)
Article
Patent abstract
A plurality of interconnect features are formed in an interconnect layer on a first insulating layer on a substrate. An opening in the first insulating layer is formed through at least one of the interconnect features. A gap fill layer is deposited in the opening.
Edits on 26 Apr, 2023
Golden AI
Infobox
Is a
Patent Applicant
Current Assignee
Patent Jurisdiction
Patent Number
105467720
Date of Patent
January 28, 2020
0Patent Application Number
160701720
Date Filed
March 30, 2016
0Patent Primary Examiner
Edits on 23 Sep, 2022
Golden AI
Infobox
Is a
Patent Applicant
Current Assignee
Patent Jurisdiction
Patent Number
105467720
Date of Patent
January 28, 2020
0Patent Application Number
160701720
Date Filed
March 30, 2016
0Patent Primary Examiner
Edits on 1 Feb, 2022
Golden AI
Edits made to:
Infobox (+9 properties)
US Patent 10546772 Self-aligned via below subtractively patterned interconnect
Infobox
Is a
Patent applicant
Current assignee
Patent jurisdiction
Patent number
10546772
Date of patent
January 28, 2020
Patent application number
16070172
Date Filed
March 30, 2016
Patent primary examiner
Find more entities like US Patent 10546772 Self-aligned via below subtractively patterned interconnect
Use the Golden Query Tool to find similar entities by any field in the Knowledge Graph, including industry, location, and more.
