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US Patent 10546957 Nanosheet FET including all-around source/drain contact
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Patent
Date Filed
January 11, 2018
Date of Patent
January 28, 2020
Patent Application Number
15868742
Patent Citations
US Patent 10032867 Forming bottom isolation layer for nanosheet technology
US Patent 10249541 Forming a hybrid channel nanosheet semiconductor structure
US Patent 10243054 Integrating standard-gate and extended-gate nanosheet transistors on the same substrate
US Patent 10276442 Wrap-around contacts formed with multiple silicide layers
US Patent 10263100 Buffer regions for blocking unwanted diffusion in nanosheet transistors
US Patent 10002939 Nanosheet transistors having thin and thick gate dielectric material
Patent Citations Received
US Patent 11973129 Semiconductor device structure with inner spacer layer and method for forming the same
0
US Patent 11508823 Low capacitance low RC wrap-around-contact
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
10546957
Patent Primary Examiner
Alexander O Williams
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