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US Patent 10643011 Automatic design and verification of safety critical electronic systems

Patent 10643011 was granted and assigned to Cadence Design Systems on May, 2020 by the United States Patent and Trademark Office.

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Patent Citations Received
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US Patent 12124789 Multi-stage electronic design automation parameter tuning
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US Patent 11842134 Automated determinaton of failure mode distribution
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US Patent 11709767 Method and apparatus for verifying operation state of application
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https://pdfpiw.uspto.gov/.piw?Docid=106430110
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US Patent 11651134 Method of certifying safety levels of semiconductor memories in integrated circuits
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US Patent 11630938 Failure mode analysis for circuit design
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US Patent 11422185 System and method for testing critical components on system-on-chip
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US Patent 11042688 Method of certifying safety levels of semiconductor memories in integrated circuits
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US Patent 10853545 Automatic gate-level FS analysis and FMEDA
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 US Patent 10643011 Automatic design and verification of safety critical electronic systems

Infobox
Is a
Patent
Patent
Patent applicant
Cadence Design Systems
Cadence Design Systems
Current assignee
Cadence Design Systems
Cadence Design Systems
Patent jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent number
10643011
Date of patent
May 5, 2020
Patent application number
16023937
Date Filed
June 29, 2018
Patent primary examiner
‌
Mohammed Alam

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