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US Patent 10734286 Multiple dielectrics for gate-all-around transistors

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US Patent 11664656 ESD protection for integrated circuit devices
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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=107342860
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Infobox
Is a
Patent
Patent
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
107342860
Date of Patent
August 4, 2020
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Patent Application Number
162701740
Date Filed
February 7, 2019
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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=107342860
Patent Citations
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US Patent 10103065 Gate metal patterning for tight pitch applications
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US Patent 10410933 Replacement metal gate patterning for nanosheet devices
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US Patent 10475902 Spacers for nanowire-based integrated circuit device and method of fabricating same
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US Patent 10566245 Method of fabricating gate all around semiconductor device
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US Patent 10566248 Work function metal patterning for N-P spaces between active nanostructures using unitary isolation pillar
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US Patent 10566435 Gate stack quality for gate-all-around field-effect transistors
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US Patent 10573521 Gate metal patterning to avoid gate stack attack due to excessive wet etching
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Patent Citations Received
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US Patent 11056396 Gate-all-around devices having gate dielectric layers of varying thicknesses and method of forming the same
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US Patent 11302692 Semiconductor devices having gate dielectric layers of varying thicknesses and methods of forming the same
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US Patent 11368016 ESD protection for integrated circuit devices
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Patent Primary Examiner
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US Patent 11368016 ESD protection for integrated circuit devices
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Website URL
https://pdfpiw.uspto.gov/.piw?Docid=10734286
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