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US Patent 10763865 Field programmable gate array with internal phase-locked loop

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US Patent 12130770 Apparatus for synchronous ethernet
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US Patent 12113539 Field programmable gate array with external phase-locked loop
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US Patent 12107587 Field programmable gate array with internal phase-locked loop
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US Patent 12021538 Clock frequency limiter
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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=1076386500
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https://pdfpiw.uspto.gov/.piw?Docid=10763865
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US Patent 11329655 Field programmable gate array with internal phase-locked loop
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US Patent 11018678 Field programmable gate array with internal phase-locked loop
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 US Patent 10763865 Field programmable gate array with internal phase-locked loop

Infobox
Is a
Patent
Patent
Patent jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent number
10763865
Date of patent
September 1, 2020
Patent application number
16888218
Date Filed
May 29, 2020
Patent citations
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US Patent 10411720 Efficient and dependable clock synchronization in hardware
Patent primary examiner
‌
Kevin M Burd

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