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US Patent 10825740 Low resistance source-drain contacts using high temperature silicides

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
0
Date Filed
December 27, 2017
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Date of Patent
November 3, 2020
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Patent Application Number
15855049
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Patent Citations
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US Patent 10032897 Single electron transistor with self-aligned Coulomb blockade
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US Patent 10090392 Semiconductor device and manufacturing method thereof
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US Patent 10153372 High mobility strained channels for fin-based NMOS transistors
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US Patent 10109507 Fluorine contamination control in semiconductor manufacturing process
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US Patent 10157995 Integrating junction formation of transistors with contact formation
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US Patent 10011920 Low-temperature selective epitaxial growth of silicon for device integration
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US Patent 10032889 Self-aligned passivation of active regions
Patent Citations Received
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US Patent 12020937 Carbon implantation for thicker gate silicide
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
10825740
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Patent Primary Examiner
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Jay C Kim
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