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US Patent 10991804 Transistor level interconnection methodologies utilizing 3D interconnects

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
February 1, 2019
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Date of Patent
April 27, 2021
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Patent Application Number
16265456
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Patent Citations Received
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US Patent 12136605 Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics and method for forming the same
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US Patent 12080672 Direct gang bonding methods including directly bonding first element to second element to form bonded structure without adhesive
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US Patent 12113054 Non-volatile dynamic random access memory
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US Patent 12113056 Stacked dies and methods for forming bonded structures
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US Patent 12125784 Interconnect structures
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US Patent 12132020 Low temperature bonded structures
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US Patent 11621246 Diffused bitline replacement in stacked wafer memory
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US Patent 11626363 Bonded structures with integrated passive component
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US Patent 11631586 Heterogeneous annealing method
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US Patent 11631647 Integrated device packages with integrated device die and dummy element
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•••
Patent Inventor Names
Javier A. Delacruz
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David Edward Fisch
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
10991804
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Patent Primary Examiner
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Moin M Rahman
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