US Patent 11056411 Chip packaging structure

A chip packaging structure with better reliability includes a first protective layer, a redistribution layer formed on the first protective layer, at least one chip electrically connected to the redistribution layer, and an encapsulating layer covering the redistribution layer, the chip, and the side surfaces of the first protective layer. The first protective layer comprises an exposed surface and at least four side surfaces each connected to the exposed surface. A plurality of second openings is defined in the second protective layer, and a portion of the redistribution layer is exposed from the plurality of second openings.