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US Patent 11362235 Substrate structuring methods

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Infobox
Patent Citations
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US Patent 10229827 Method of redistribution layer formation for advanced packaging applications
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Infobox
Is a
Patent
Patent
0
Patent Applicant
Applied Materials
Applied Materials
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Current Assignee
Applied Materials
Applied Materials
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
113622350
Date of Patent
June 14, 2022
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Patent Application Number
172277630
Date Filed
April 12, 2021
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Patent Citations
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US Patent 10014292 3D semiconductor device and structure
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US Patent 10037975 Semiconductor device package and a method of manufacturing the same
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US Patent 10053359 Microelectronic packages having axially-partitioned hermetic cavities and methods for the fabrication thereof
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US Patent 10090284 Semiconductor device and method of manufacture
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US Patent 10109588 Electronic component package and package-on-package structure including the same
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US Patent 10128177 Multi-layer package with integrated antenna
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US Patent 10153219 Fan out wafer level package type semiconductor package and package on package type semiconductor package including the same
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US Patent 10163803 Integrated fan-out packages and methods of forming the same
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US Patent 10170386 Electronic component package and method of manufacturing the same
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US Patent 10177083 Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages
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US Patent 10211072 Method of reconstituted substrate formation for advanced packaging applications
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US Patent 10229827 Method of redistribution layer formation for advanced packaging applications
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US Patent 10256180 Package structure and manufacturing method of package structure
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US Patent 10269773 Semiconductor packages and methods of forming the same
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US Patent 10297518 Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package
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US Patent 10297586 Methods for processing a 3D semiconductor device
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US Patent 10304765 Semiconductor device package
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US Patent 10347585 Fan-out semiconductor package
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US Patent 10410971 Thermal and electromagnetic interference shielding for die embedded in package substrate
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US Patent 10424530 Electrical interconnections with improved compliance due to stress relaxation and method of making
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US Patent 10515912 Integrated circuit packages
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US Patent 10522483 Package assembly for embedded die and associated techniques and configurations
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US Patent 10553515 Integrated circuit structures with extended conductive pathways
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US Patent 10570257 Copolymerized high temperature bonding component
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US Patent 10658337 Packages and packaging methods for semiconductor devices, and packaged semiconductor devices
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Patent Primary Examiner
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Earl N Taylor
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CPC Code
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H01L 21/0275
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Y02E 10/547
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H01L 23/49827
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H01L 2221/68345
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H01L 21/76898
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H01L 31/1892
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H01L 31/1804
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H01L 21/6835
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H01L 21/486
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H01L 21/3086
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H01L 21/30621
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H01L 21/3046
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Edits on 1 Apr, 2023
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Edits on 31 Mar, 2023
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