US Patent 11368016 ESD protection for integrated circuit devices

Patent

US Patent 10692866 Co-integrated channel and gate formation scheme for nanosheet transistors having separately tuned threshold voltages

US Patent 10672868 Methods of forming self aligned spacers for nanowire device structures

US Patent 10679906 Method of forming nanosheet transistor structures with reduced parasitic capacitance and improved junction sharpness

US Patent 10680107 Nanosheet transistor with stable structure

US Patent 10692873 Gate formation scheme for nanosheet transistors having different work function metals and different nanosheet width dimensions

US Patent 10692985 Protection of high-K dielectric during reliability anneal on nanosheet structures

US Patent 10714391 Method for controlling transistor delay of nanowire or nanosheet transistor devices

US Patent 10727315 Nanosheet transistor

US Patent 10734273 Semiconductor device including isolation layers and method of manufacturing the same

US Patent 10734286 Multiple dielectrics for gate-all-around transistors

US Patent 11955171 Integrated circuit device including an SRAM portion having end power select circuits

US Patent 11569222 Low-voltage electrostatic discharge (ESD) protection circuit, integrated circuit and method for ESD protection thereof

US Patent 12119641 ESD protection for integrated circuit devices

US Patent 11972793 Integrated circuit device including an SRAM portion having end power select circuits

US Patent 11973342 ESD protection for integrated circuit devices

United States Patent and Trademark Office

Dharti H Patel

H01L 27/0266

H02H 9/046

H01L 27/0262

H01L 27/0255

H01L 27/0292

H01L 27/0288

H01L 27/0296