US Patent 11368016 ESD protection for integrated circuit devices

US Patent 10049882 Method for fabricating semiconductor device including forming a dielectric layer on a structure having a height difference using ALD

US Patent 10050107 Nanosheet transistors on bulk material

US Patent 10074575 Integrating and isolating nFET and pFET nanosheet transistors on a substrate

US Patent 10103065 Gate metal patterning for tight pitch applications

US Patent 10109533 Nanosheet devices with CMOS epitaxy and method of forming

US Patent 10128215 Package including a plurality of stacked semiconductor devices having area efficient ESD protection

US Patent 10134720 Package including a plurality of stacked semiconductor devices having area efficient ESD protection

US Patent 10229971 Integration of thick and thin nanosheet transistors on a single chip

US Patent 10242920 Integrating and isolating NFET and PFET nanosheet transistors on a substrate

US Patent 10243054 Integrating standard-gate and extended-gate nanosheet transistors on the same substrate

US Patent 10243061 Nanosheet transistor

US Patent 10263075 Nanosheet CMOS transistors

US Patent 10263100 Buffer regions for blocking unwanted diffusion in nanosheet transistors

US Patent 10290549 Integrated circuit structure, gate all-around integrated circuit structure and methods of forming same

US Patent 10283516 Stacked nanosheet field effect transistor floating-gate EEPROM cell and array

US Patent 10297664 Nanosheet transistor with uniform effective gate length

US Patent 10304936 Protection of high-K dielectric during reliability anneal on nanosheet structures

US Patent 10332809 Method and structure to introduce strain in stack nanosheet field effect transistor

US Patent 10332986 Formation of inner spacer on nanosheet MOSFET

US Patent 10347719 Nanosheet transistors on bulk material

US Patent 10374089 Tensile strain in NFET channel

US Patent 10366931 Nanosheet devices with CMOS epitaxy and method of forming

US Patent 10366970 3D semiconductor device and structure

US Patent 10367062 Co-integration of silicon and silicon-germanium channels for nanosheet devices

US Patent 10381068 Ultra dense and stable 4T SRAM cell design having NFETs and PFETs

US Patent 10381273 Vertically stacked multi-channel transistor structure

US Patent 10388646 Electrostatic discharge protection devices including a field-induced switching element

US Patent 10396169 Nanosheet transistors having different gate dielectric thicknesses on the same chip

US Patent 10410927 Method and structure for forming transistors with high aspect ratio gate without patterning collapse

US Patent 10410931 Fabricating method of nanosheet transistor spacer including inner spacer

US Patent 10410933 Replacement metal gate patterning for nanosheet devices

US Patent 10418346 Package including a plurality of stacked semiconductor devices having area efficient ESD protection

US Patent 10418449 Circuits based on complementary field-effect transistors

US Patent 10418493 Tight pitch stack nanowire isolation

US Patent 10424639 Nanosheet transistor with high-mobility channel

US Patent 10424651 Forming nanosheet transistor using sacrificial spacer and inner spacers

US Patent 10431651 Nanosheet transistor with robust source/drain isolation from substrate

US Patent 10446664 Inner spacer formation and contact resistance reduction in nanosheet transistors

US Patent 10439049 Nanosheet device with close source drain proximity

US Patent 10475815 Three dimension integrated circuits employing thin film transistors

US Patent 10490559 Gate formation scheme for nanosheet transistors having different work function metals and different nanosheet width dimensions

US Patent 10504890 High density nanosheet diodes

US Patent 10515935 3D semiconductor device and structure

US Patent 10529739 Asymmetric band gap junctions in narrow band gap MOSFET

US Patent 10535733 Method of forming a nanosheet transistor

US Patent 10539528 Stacked nanofluidics structure

US Patent 10546878 Asymmetric junction engineering for narrow band gap MOSFET

US Patent 10546942 Nanosheet transistor with optimized junction and cladding defectivity control

US Patent 10553495 Nanosheet transistors with different gate dielectrics and workfunction metals

US Patent 10566438 Nanosheet transistor with dual inner airgap spacers

US Patent 10566443 Nanosheet transitor with optimized junction and cladding defectivity control

US Patent 10566445 Gate spacer and inner spacer formation for nanosheet transistors having relatively small space between gates

US Patent 10600638 Nanosheet transistors with sharp junctions

US Patent 10600694 Gate metal patterning for tight pitch applications

US Patent 10600889 Nanosheet transistors with thin inner spacers and tight pitch gate

US Patent 10615256 Nanosheet transistor gate structure having reduced parasitic capacitance

US Patent 10615257 Patterning method for nanosheet transistors

US Patent 10622208 Lateral semiconductor nanotube with hexagonal shape

US Patent 10643899 Gate stack optimization for wide and narrow nanosheet transistor devices

US Patent 10658459 Nanosheet transistor with robust source/drain isolation from substrate

US Patent 10658493 Gate spacer and inner spacer formation for nanosheet transistors having relatively small space between gates

US Patent 10665669 Insulative structure with diffusion break integral with isolation layer and methods to form same

US Patent 10672868 Methods of forming self aligned spacers for nanowire device structures

US Patent 10679906 Method of forming nanosheet transistor structures with reduced parasitic capacitance and improved junction sharpness

US Patent 10680107 Nanosheet transistor with stable structure

US Patent 10692866 Co-integrated channel and gate formation scheme for nanosheet transistors having separately tuned threshold voltages

US Patent 10692873 Gate formation scheme for nanosheet transistors having different work function metals and different nanosheet width dimensions

US Patent 10692985 Protection of high-K dielectric during reliability anneal on nanosheet structures

US Patent 10714391 Method for controlling transistor delay of nanowire or nanosheet transistor devices

US Patent 10727315 Nanosheet transistor

US Patent 10734273 Semiconductor device including isolation layers and method of manufacturing the same

US Patent 10734286 Multiple dielectrics for gate-all-around transistors

US Patent 10734523 Nanosheet substrate to source/drain isolation

US Patent 10734525 Gate-all-around transistor with spacer support and methods of forming same

US Patent 10756175 Inner spacer formation and contact resistance reduction in nanosheet transistors

US Patent 10756613 Controlling current flow between nodes with adjustable back-gate voltage

US Patent 10790277 Semiconductor device

US Patent 10790281 Stacked channel structures for MOSFETs

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