US Patent 11638377 Self-aligned select gate cut for 3D NAND

Electronic devices and methods of forming the electronic devices are described. The electronic devices comprise a plurality of memory holes extending along a first direction through a plurality of alternating oxide and nitride layers. Each memory hole has a core oxide surrounded by a semiconductor material, the semiconductor material surrounded by a dielectric. The memory holes are staggered to provide a plurality of memory hole lines having spaced memory holes so that adjacent memory hole lines have the memory holes in a staggered configuration. A conductive material is on top of the stack of alternating oxide and nitride layers. A dielectric filled cut line extends through the conductive material in a direction across the plurality of memory hole lines. The dielectric filled cut line separates a first memory hole line from an adjacent second memory hole line without disabling the functionality of the memory holes.