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US Patent 11658085 Integrated circuit package and method
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Patent
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Current Assignee
Taiwan Semiconductor Manufacturing Company
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Date Filed
January 3, 2022
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Date of Patent
May 23, 2023
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Patent Applicant
Taiwan Semiconductor Manufacturing Company
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Patent Application Number
17567519
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Patent Citations
US Patent 10665520 Integrated circuit package and method
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US Patent 9997464 Dummy features in redistribution layers (RDLS) and methods of forming same
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US Patent 8680647 Packages with passive devices and methods of forming the same
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US Patent 8703542 Wafer-level packaging mechanisms
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US Patent 8759964 Wafer level package structure and fabrication methods
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US Patent 8829676 Interconnect structure for wafer level package
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US Patent 9741690 Redistribution layers in semiconductor packages and methods of forming same
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11658085
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Patent Primary Examiner
Victor A Mandala
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CPC Code
H01L 23/49827
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H01L 23/5386
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H01L 23/528
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H01L 23/5226
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H01L 23/3121
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H01L 23/525
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H01L 2224/18
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H01L 2224/48227
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H01L 2924/181
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H01L 23/481
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