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US Patent 11748550 Integrated circuit with constrained metal line arrangement
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Patent
Date Filed
June 8, 2021
Date of Patent
September 5, 2023
Patent Application Number
17342006
Patent Citations
US Patent 9256709 Method for integrated circuit mask patterning
US Patent 7260442 Method and system for mask fabrication process control
US Patent 7222322 Method and mechanism for implementing tessellation-based routing
Patent Inventor Names
XinYong Wang
Li-Chun Tien
Qiquan Wang
Yuan Ma
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
11748550
Patent Primary Examiner
Nghia M Doan
CPC Code
H01L 27/0207
H01L 21/76838
H01L 21/76877
H01L 23/528
H01L 2027/11875
H01L 27/11807
H05K 1/0268
G06F 30/394
G06F 30/398
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