US Patent 11783900 Erase method of non-volatile memory device

A non-volatile memory device includes a memory cell array including a plurality of cell strings, each of the plurality of cell strings includes a gate-induced drain leakage (GIDL) transistor and a memory cell group, and a control logic to apply a voltage to each of the plurality of cell strings. The control logic performs a first erase operation of erasing the memory cell groups of each of the plurality of cell strings, a first verification operation of detecting erase results of the memory cell groups of each of the plurality of cell strings, and a program operation of programming the GIDL transistors of some of the plurality of cell strings.