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US Patent 11804419 Semiconductor device
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Patent
Date Filed
February 25, 2021
Date of Patent
October 31, 2023
Patent Application Number
17185166
Patent Citations
US Patent 8487444 Three-dimensional system-in-package architecture
US Patent 8916471 Method for forming semiconductor structure having through silicon via for signal and shielding structure
US Patent 9048151 Self-powered integrated circuit with photovoltaic cell
US Patent 9093348 Method of manufacturing semiconductor device, semiconductor device, and electronic apparatus
US Patent 9293366 Through-substrate vias with improved connections
US Patent 9293418 Backside through vias in a bonded structure
US Patent 9343390 TSV formation processes using TSV-last approach
US Patent 9299640 Front-to-back bonding with through-substrate via (TSV)
US Patent 9691684 Integrated circuit device including through-silicon via structure and decoupling capacitor and method of manufacturing the same
US Patent 8164165 Wafer-to-wafer stack with supporting pedestal
•••
Patent Inventor Names
Hakseung Lee
Kwangjin Moon
Hyungjun Jeon
Hyoukyung Cho
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
11804419
Patent Primary Examiner
Jaehwan Oh
CPC Code
H01L 24/08
H01L 23/5283
H01L 25/0657
H01L 23/481
H01L 23/5226
H01L 21/76898
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