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US Patent 11835991 Self-test controller, and associated method

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 US Patent 11835991 Self-test controller, and associated method

Article

Patent abstract

In an embodiment, a method for managing self-tests in an integrated circuit (IC) includes: receiving built-in-self-test (BIST) configuration data; configuring a first clock to a first frequency based on the BIST configuration data; performing a first BIST test at the first frequency; configuring a second clock to a second frequency that is different from the first frequency; and performing a second BIST test at the second frequency.

Infobox
Is a
Patent
Patent
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
118359910
Patent Inventor Names
Amritanshu Anand0
Amulya Pandey0
Balwinder Singh Soni0
Venkata Narayanan Srinivasan0
Date of Patent
December 5, 2023
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Patent Application Number
172089350
Date Filed
March 22, 2021
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Patent Citations
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US Patent 7134061 At-speed ATPG testing and apparatus for SoC designs having multiple clock domain using a VLCT test platform
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US Patent 7356741 Modular test controller with BIST circuit for testing embedded DRAM circuits
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US Patent 7360134 Centralized BIST engine for testing on-chip memory structures
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US Patent 7716546 System and method for improved LBIST power and run time
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US Patent 7761763 System-on-chip (SOC) having built-in-self-test circuits and a self-test method of the SOC
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US Patent 7831877 Circuitry to prevent peak power problems during scan shift
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US Patent 7945823 Programmable address space built-in self test (BIST) device and method for fault detection
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US Patent 7996743 Logic circuit testing with reduced overhead
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US Patent 8694276 Built-in self-test methods, circuits and apparatus for concurrent test of RF modules with a dynamically configurable test structure
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US Patent 8935586 Staggered start of BIST controllers and BIST engines
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US Patent 9196381 Technique to operate memory in functional mode under LBIST test
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US Patent 11218153 Configurable built-in self-test for an all digital phase locked loop
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US Patent 9823296 Built-in self test system, system on a chip and method for controlling built-in self tests
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US Patent 10191110 Apparatus and method for self-testing an integrated circuit
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US Patent 10802077 Test circuit for dynamic checking for faults on functional and BIST clock paths to memory in both ATPG and LBIST modes
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US Patent 10823781 Internally clocked logic built-in self-test apparatuses and methods
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Patent Primary Examiner
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Kamini B Patel
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CPC Code
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G06F 11/26
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G06F 11/27
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G06F 1/3296
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G06F 1/324
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G06F 1/08
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