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US Patent 11855064 Techniques for processing devices

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
0
Date Filed
June 10, 2021
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Date of Patent
December 26, 2023
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Patent Application Number
17344100
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Patent Citations
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US Patent 10886177 3D chip with shared clock distribution network
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US Patent 10998292 Offset pads over TSV
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US Patent 11004757 Bonded structures
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US Patent 11011494 Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
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US Patent 11011503 Direct-bonded optoelectronic interconnect for high-density integrated photonics
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US Patent 11031285 Diffusion barrier collar for interconnects
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US Patent 11037919 Techniques for processing devices
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US Patent 11056348 Bonding surfaces for microelectronics
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US Patent 11069734 Image sensor device
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US Patent 11176450 Three dimensional circuit implementing machine trained network
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•••
Patent Inventor Names
Gaius Gillman Fountain, Jr.
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Guilian Gao
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Cyprian Emeka Uzoh
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Laura Wills Mirkarimi
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11855064
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Patent Primary Examiner
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Brook Kebede
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CPC Code
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H01L 24/83
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H01L 25/0657
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H01L 25/50
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H01L 24/30
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H01L 24/27
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H01L 21/78
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H01L 21/6836
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H01L 21/187
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