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US Patent 11855064 Techniques for processing devices

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 US Patent 11855064 Techniques for processing devices

Article

Patent abstract

Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.

Infobox
Is a
Patent
Patent
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
118550640
Patent Inventor Names
Cyprian Emeka Uzoh0
Gaius Gillman Fountain, Jr.0
Guilian Gao0
Laura Wills Mirkarimi0
Date of Patent
December 26, 2023
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Patent Application Number
173441000
Date Filed
June 10, 2021
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Patent Citations
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US Patent 9142517 Hybrid bonding mechanisms for semiconductor wafers
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US Patent 9184125 Heterogeneous annealing method and device
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US Patent 9230941 Bonding structure for stacked semiconductor devices
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US Patent 9299736 Hybrid bonding with uniform pattern density
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US Patent 9312229 Hybrid bonding with air-gap structure
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US Patent 9331149 Method for low temperature bonding and bonded structure
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US Patent 9337235 Method and apparatus for image sensor packaging
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US Patent 9385024 Room temperature metal direct bonding
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US Patent 9394161 MEMS and CMOS integration with low-temperature bonding
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US Patent 9431368 Three dimensional device integration method and integrated device
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US Patent 9443796 Air trench in packages incorporating hybrid bonding
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US Patent 9461007 Wafer-to-wafer bonding structure
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US Patent 9476898 Sensor device and manufacturing method thereof
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US Patent 9496239 Nitride-enriched oxide-to-oxide 3D wafer bonding
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US Patent 9536848 Bond pad structure for low temperature flip chip bonding
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US Patent 9559081 Independent 3D stacking
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US Patent 9620481 Substrate bonding with diffusion barrier structures
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US Patent 9656852 CMOS-MEMS device structure, bonding mesa structure and associated method
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US Patent 9723716 Contact pad structure, an electronic component, and a method for manufacturing a contact pad structure
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US Patent 9728521 Hybrid bond using a copper alloy for yield improvement
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US Patent 9741620 Structures and methods for reliable packages
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US Patent 9799587 Semiconductor device
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US Patent 9852988 Increased contact alignment tolerance for direct bonding
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US Patent 9893004 Semiconductor interposer integration
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US Patent 9929050 Mechanisms for forming three-dimensional integrated circuit (3DIC) stacking structure
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US Patent 9941241 Method for wafer-wafer bonding
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US Patent 9941243 Wafer-to-wafer bonding structure
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US Patent 9953941 Conductive barrier direct hybrid bonding
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US Patent 9960142 Hybrid bonding with air-gap structure
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US Patent 9971777 Smart archiving of real-time performance monitoring data
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US Patent 10002844 Bonded structures
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US Patent 10026605 Method of reducing residual contamination in singulated semiconductor die
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US Patent 10075657 Edgeless large area camera system
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US Patent 10204893 Stacked dies and methods for forming bonded structures
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US Patent 10269756 Die processing
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US Patent 10269853 Image sensor device
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US Patent 10418277 Air gap spacer formation for nano-scale semiconductor devices
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US Patent 10446456 Integrated circuits protected by substrates with cavities, and methods of manufacture
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US Patent 10508030 Seal for microelectronic assembly
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US Patent 10515925 Die processing
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US Patent 10522499 Bonded structures
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US Patent 10566219 Chip transfer member, chip transfer apparatus, and chip transfer method
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US Patent 10707087 Processing stacked substrates
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US Patent 10714449 Die processing
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US Patent 10727219 Techniques for processing devices
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US Patent 10784191 Interface structures and methods for forming same
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US Patent 10790262 Low temperature bonded structures
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US Patent 10840135 Flat metal features for microelectronics applications
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US Patent 10840205 Chemical mechanical polishing for hybrid bonding
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US Patent 10854578 Diffused bitline replacement in stacked wafer memory
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US Patent 10879212 Processed stacked dies
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US Patent 10886177 3D chip with shared clock distribution network
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US Patent 10892246 Structures and methods for low temperature bonding using nanoparticles
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US Patent 10923408 Cavity packages
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US Patent 10923413 Hard IP blocks with physically bidirectional passageways
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US Patent 10937755 Bond pads for low temperature hybrid bonding
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US Patent 11011503 Direct-bonded optoelectronic interconnect for high-density integrated photonics
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US Patent 11031285 Diffusion barrier collar for interconnects
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US Patent 11037919 Techniques for processing devices
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US Patent 11056348 Bonding surfaces for microelectronics
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US Patent 11069734 Image sensor device
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US Patent 11256004 Direct-bonded lamination for improved image clarity in optical devices
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US Patent 11264357 Mixed exposure for large die
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US Patent 6887769 Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
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US Patent 6908027 Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening process
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US Patent 7045453 Very low effective dielectric constant interconnect structures and methods for fabricating the same
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Patent Primary Examiner
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Brook Kebede
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CPC Code
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H01L 25/50
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H01L 25/0657
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H01L 24/83
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H01L 24/30
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H01L 24/27
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H01L 21/78
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H01L 21/6836
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H01L 21/187
0

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