Patent attributes
A method is provided for thinning a wafer, for example a wafer containing Through Silicon Vias (TSV). The method includes providing a bonding wafer coupled to a handling wafer, and performing a wafer edge trimming process that forms a trimmed bonding wafer, where the wafer edge trimming process removes an edge portion of the bonding wafer and exposes an upper surface of the handling wafer. The method further includes forming a protective mask on the trimmed bonding wafer and on the exposed upper surface of the handling wafer, planarizing the protective mask and the trimmed bonding wafer, and selectively removing the planarized protective mask by an etching process. In one embodiment, the removing includes performing a first wet etching process that selectively removes a portion of the planarized trimmed bonding wafer relative to the planarized protective mask, and performing a second wet etching process that selectively removes the planarized protective mask.
