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US Patent 9461007 Wafer-to-wafer bonding structure

Patent 9461007 was granted and assigned to SAMSUNG ELECTRONICS CO., LTD. on October, 2016 by the United States Patent and Trademark Office.

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Is a
Patent
Patent
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Patent attributes

Current Assignee
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
94610070
Patent Inventor Names
Ju-il Choi0
Pil-kyu Kang0
Byung-lyul Park0
Jae-hwa Park0
Jin-ho Chun0
Date of Patent
October 4, 2016
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Patent Application Number
147965060
Date Filed
July 10, 2015
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Patent Citations Received
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US Patent 12136605 Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics and method for forming the same
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US Patent 12068278 Processed stacked dies
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US Patent 12074092 Hard IP blocks with physically bidirectional passageways
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US Patent 12080672 Direct gang bonding methods including directly bonding first element to second element to form bonded structure without adhesive
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US Patent 12113056 Stacked dies and methods for forming bonded structures
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US Patent 12113054 Non-volatile dynamic random access memory
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US Patent 12125784 Interconnect structures
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Patent Primary Examiner
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Alexander Oscar Williams
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Patent abstract

A wafer-to-wafer bonding structure may include: a first wafer including a first insulating layer on a first substrate and on a first copper (Cu) pad that penetrates the first insulating layer and has portions protruding from an upper surface of the first insulating layer, and a first barrier metal layer on a lower surface and sides of the first Cu pad; a second wafer including a second insulating layer on a second substrate and on a second copper (Cu) pad that penetrates the second insulating layer, has portions protruding from an upper surface of the second insulating layer, and is bonded to the first Cu pad, and a second barrier metal layer on a lower surface and sides of the second Cu pad; and a polymer layer covering protruding sides of the first and second barrier metal layers and disposed between the first and second wafers.

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