Patent attributes
Method for testing an integrated circuit device, by defect modelling of the integrated circuit device, fault modelling of the integrated circuit device based on the information obtained from the defect modelling, test development based on information obtained from the fault modelling, and executing the test on the integrated circuit device. Defect modelling of the integrated circuit device including executing a physical defect analysis of the integrated circuit device to provide a set of effective technology parameters modified from a set of defect-free technology parameters associated with the integrated circuit device, and executing an electrical modelling of the integrated circuit device using the set of effective technology parameters to provide a defect-parametrized electrical model based on a defect-free electrical model of the integrated circuit device. The present methods allow parts-per-billion testing capabilities.
