US Patent 11984401 Stacked FET integration with BSPDN

A semiconductor device including a hybrid contact scheme for stacked FET is disclosed with integration of a BSPDN. A double-sided (both frontside and backside of the wafer) contact scheme with buried power rail (BPR) and backside power distribution network (BSPDN) provides optimum contact and interconnect. The stacked FET could include, for example, FINFET over FINFET, FINFET over nanosheet, or nanosheet over nanosheet.