US Patent 11984401 Stacked FET integration with BSPDN
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US Patent 11984401 Stacked FET integration with BSPDN
Article
Patent abstract
A semiconductor device including a hybrid contact scheme for stacked FET is disclosed with integration of a BSPDN. A double-sided (both frontside and backside of the wafer) contact scheme with buried power rail (BPR) and backside power distribution network (BSPDN) provides optimum contact and interconnect. The stacked FET could include, for example, FINFET over FINFET, FINFET over nanosheet, or nanosheet over nanosheet.
Infobox
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Patent Jurisdiction
Patent Number
Patent Inventor Names
Dechao Guo0
Junli Wang0
Mukta Ghate Farooq0
Ruilong Xie0
Date of Patent
May 14, 2024
0Patent Application Number
173044600
Date Filed
June 22, 2021
0Patent Citations
Patent Primary Examiner
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