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US Patent 11984401 Stacked FET integration with BSPDN
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Patent
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Date Filed
June 22, 2021
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Date of Patent
May 14, 2024
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Patent Application Number
17304460
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Patent Citations
US Patent 10388519 Method and device for incorporating single diffusion break into nanochannel structures of FET devices
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US Patent 10586765 Buried power rails
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Patent Inventor Names
Mukta Ghate Farooq
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Ruilong Xie
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Junli Wang
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Dechao Guo
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11984401
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Patent Primary Examiner
Reema Patel
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CPC Code
H01L 29/78696
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H01L 29/42392
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H01L 29/41733
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H01L 27/0924
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H01L 27/0922
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H01L 23/5286
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