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US Patent 12067335 Automatic configuration of pipeline modules in an electronics system

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 US Patent 12067335 Automatic configuration of pipeline modules in an electronics system

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Patent abstract

Generation of a full register-transfer level (RTL) description of an electronics system includes generating an optimized pipeline configuration from inputs including a database of RTL elements, and a list of configurable pipeline components; and generating the full RTL description with the pipeline components configured according to the optimized pipeline configuration. Generating the configuration includes performing a search for a configuration that optimizes area and timing.

Infobox
Is a
Patent
Patent
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
120673350
Patent Inventor Names
Benoit de Lescure0
Mokhtar Hirech0
Date of Patent
August 20, 2024
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Patent Application Number
177171330
Date Filed
April 11, 2022
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Patent Citations
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US Patent 7096436 Macro design techniques to accommodate chip level wiring and circuit placement across the macro
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US Patent 7398497 Electronic circuit designing method apparatus for designing an electronic circuit, and storage medium for storing an electronic circuit designing method
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US Patent 7587687 System and method for incremental synthesis
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US Patent 7788625 Method and apparatus for precharacterizing systems for use in system level design of integrated circuits
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US Patent 8042087 Method to design network-on-chip (NOC)-based communication systems
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US Patent 8302041 Implementation flow for electronic circuit designs using choice networks
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US Patent 8806410 Power balanced pipelines
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US Patent 8819611 Asymmetric mesh NoC topologies
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US Patent 9184998 Distributed path update in hybrid networks
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US Patent 9251300 Methods and tools for designing integrated circuits with auto-pipelining capabilities
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US Patent 9262359 Method and system for implementing pipeline flip-flops
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US Patent 9444702 System and method for visualization of NoC performance based on simulation output
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US Patent 9569574 Method and apparatus for performing fast incremental physical design optimization
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US Patent 9792397 System and method for designing system on chip (SoC) circuits through artificial intelligence and reinforcement learning
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US Patent 9825779 Network-on-chip (NoC) topology generation
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US Patent 9940423 Editing a NoC topology on top of a floorplan
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US Patent 10068047 Systems and methods for designing an integrated circuit
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US Patent 10089426 Logic circuit generation device and method
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US Patent 10282502 Flexible constraint integrated circuit implementation runs
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US Patent 10348563 System-on-chip (SoC) optimization through transformation and generation of a network-on-chip (NoC) topology
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US Patent 10460062 Method and computer program for determining a placement of at least one circuit for a reconfigurable logic device
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US Patent 10657210 Slack time recycling
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US Patent 10733350 On-chip and system-area multi-processor interconnection networks in advanced processes for maximizing performance minimizing cost and energy
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US Patent 10853545 Automatic gate-level FS analysis and FMEDA
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US Patent 10922471 High performance regularized network-on-chip architecture
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US Patent 10990724 System and method for incremental topology synthesis of a network-on-chip
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US Patent 11281827 Optimization of parameters for synthesis of a topology using a discriminant function module
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US Patent 11449655 Synthesis of a network-on-chip (NoC) using performance constraints and objectives
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US Patent 11675942 Optimization of parameters for synthesis of a topology using a discriminant function module
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US Patent 6883455 Personal watercraft and buffer member for personal watercraft
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US Patent 6907591 Method and apparatus for performing extraction using a neural network
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Patent Primary Examiner
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Leigh M. Garbowski
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