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US Patent 12068278 Processed stacked dies
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Patent
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Date Filed
December 29, 2022
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Date of Patent
August 20, 2024
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Patent Application Number
18148369
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Patent Citations
US Patent 10998292 Offset pads over TSV
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US Patent 11631647 Integrated device packages with integrated device die and dummy element
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US Patent 11652083 Processed stacked dies
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US Patent 11664357 Techniques for joining dissimilar materials in microelectronics
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US Patent 11749645 TSV as pad
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US Patent 11762200 Bonded optical devices
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US Patent 11764177 Bonded structure with interconnect structure
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US Patent 11842894 Electrical redundancy for bonded structures
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US Patent 11876076 Apparatus for non-volatile random access memory stacks
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US Patent 6887769 Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
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•••
Patent Inventor Names
Cyprian Emeka Uzoh
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Gaius Gillman Fountain, Jr.
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Guilian Gao
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Laura Wills Mirkarimi
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
12068278
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Patent Primary Examiner
Mounir S Amer
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CPC Code
H01L 24/83
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