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US Patent 6891234 Transistor with workfunction-induced charge layer
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Patent
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Date Filed
April 26, 2004
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Date of Patent
May 10, 2005
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Patent Application Number
10832576
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Patent Citations Received
US Patent 12074217 Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
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US Patent 11843040 MIS contact structure with metal oxide conductor
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US Patent 11870431 AC coupling modules for bias ladders
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US Patent 12081211 High power positive logic switch
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US Patent 11978799 Method for fabricating transistor with thinned channel
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Patent Inventor Names
Daniel J. Connelly
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Carl Faulkner
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Daniel E. Grupp
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
6891234
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Patent Primary Examiner
Sara Crane
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