US Patent 7105931 Electronic package and method

An electronic package substrate for an electronic package that includes an adhesive bonding member having two planar surfaces and an orifice there through for receiving a chip and a circuitized member having two planar surfaces, one surface being bonded to one of the planar surfaces of the bonding member, the circuitized member being electrically connectable to the chip. The electronic package substrate is fabricated for an electronic package for either a wire bonded chip, a tab bonded chip, or a flip chip.