US Patent 7193279 Non-planar MOS structure with a strained channel region
Patent 7193279 was granted and assigned to Intel on March, 2007 by the United States Patent and Trademark Office.
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Patent Inventor Names
Been-Yih Jin0
Brian S. Doyle0
Robert Chau0
Suman Datta0
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Patent abstract
An embodiment is a non-planar MOS transistor structure including a strained channel region. The combination of a non-planar MOS transistor structure, and in particular an NMOS tri-gate transistor, with the benefits of a strained channel yields improved transistor drive current, switching speed, and decreased leakage current for a given gate length width versus a non-planar MOS structure with an unstrained channel or planar MOS structure including a strained channel.
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US Patent 07193279 Non-planar MOS structure with a strained channel region US Patent 7193279 Non-planar MOS structure with a strained channel region
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Patent Number
071932790
Patent Number
71932790
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Current Assignee
Patent Jurisdiction
Patent Number
071932790
Date of Patent
March 20, 2007
0Patent Application Number
110391970
Date Filed
January 18, 2005
0Official Website
Patent Primary Examiner
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US Patent 07193279 Non-planar MOS structure with a strained channel region
Infobox
Is a
Current assignee
Patent jurisdiction
Patent number
07193279
Date of patent
March 20, 2007
Patent application number
11039197
Date Filed
January 18, 2005
Patent primary examiner
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