US Patent 7229745 Lithographic semiconductor manufacturing using a multi-layered process
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Patent Inventor Names
Philip A. Lamarre0
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Patent abstract
Multilayer resist systems and techniques used for liftoff or planarizing topography wherein the dimensions and thicknesses of the layers are independently controlled. The undercut may also be independently controlled for precision structures.
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US Patent 07229745 Lithographic semiconductor manufacturing using a multi-layered process US Patent 7229745 Lithographic semiconductor manufacturing using a multi-layered process
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Patent Number
072297450
Patent Number
72297450
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Patent Number
072297450
Date of Patent
June 12, 2007
0Patent Application Number
107100230
Date Filed
June 14, 2004
0Official Website
Patent Primary Examiner
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US Patent 07229745 Lithographic semiconductor manufacturing using a multi-layered process
Infobox
Is a
Patent jurisdiction
Patent number
07229745
Date of patent
June 12, 2007
Patent application number
10710023
Date Filed
June 14, 2004
Patent primary examiner
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