US Patent 7364962 Shallow trench isolation process utilizing differential liners
Patent 7364962 was granted and assigned to Advanced Micro Devices on April, 2008 by the United States Patent and Trademark Office.
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Patent abstract
A method of manufacturing an integrated circuit (IC) can utilize a shallow trench isolation (STI) technique. The shallow trench isolation technique can be used in an IC process. Separate liners for the trench are used for NMOS and PMOS regions. The liners can induce strain in the substrate.
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Current Assignee
Patent Jurisdiction
Patent Number
73649620
Date of Patent
April 29, 2008
0Patent Application Number
107698350
Date Filed
February 2, 2004
0Patent Primary Examiner
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Official Website
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US Patent 07364962 Shallow trench isolation process utilizing differential liners US Patent 7364962 Shallow trench isolation process utilizing differential liners
Infobox
Patent Number
0736496200
Patent Number
736496200
Edits on 22 Mar, 2023
Golden AI
Infobox
Is a
Current Assignee
Patent Jurisdiction
Patent Number
073649620
Date of Patent
April 29, 2008
0Patent Application Number
107698350
Date Filed
February 2, 2004
0Official Website
Patent Primary Examiner
Edits on 22 Sep, 2022
Golden AI
Infobox
Is a
Current Assignee
Patent Jurisdiction
Patent Number
073649620
Date of Patent
April 29, 2008
0Patent Application Number
107698350
Date Filed
February 2, 2004
0Official Website
Patent Primary Examiner
Edits on 17 Jun, 2022
Golden AI
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US Patent 07364962 Shallow trench isolation process utilizing differential liners
Infobox
Is a
Current assignee
Patent jurisdiction
Patent number
07364962
Date of patent
April 29, 2008
Patent application number
10769835
Date Filed
February 2, 2004
Patent primary examiner
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