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US Patent 7821039 Layout architecture for improving circuit performance
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Patent
Date Filed
August 18, 2008
Date of Patent
October 26, 2010
Patent Application Number
12193354
Patent Citations Received
US Patent 11803682 Semiconductor device including standard cell having split portions
US Patent 11968821 Methods used in fabricating integrated circuitry and methods of forming 2T-1C memory cell arrays
0
US Patent 12002874 Buried power rail contact
0
US Patent 11709985 Semiconductor device including standard cells with combined active region
0
US Patent 11755813 Integrated circuit structure
US Patent 11790148 Integrated circuit and method of forming an integrated circuit
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
7821039
Patent Primary Examiner
Chuong Anh Luu
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