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US Patent 8154128 3D integrated circuit layer interconnect

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Patent Citations Received
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US Patent 12009386 Structure and method for forming integrated high density MIM capacitor
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US Patent 11967560 Integrated circuit
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US Patent 11916011 3D virtual ground memory and manufacturing methods for same
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Patent abstract

A three-dimensional 3D interconnect structure with a small footprint is described, useful for connection from above to levels of circuit structures in a multi-level device. Also, an efficient and low cost method for manufacturing the 3D interconnect structure is provided.

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Hsiang-Lan Lung0
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US Patent 11715755 Structure and method for forming integrated high density MIM capacitor
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US Patent 08154128 3D integrated circuit layer interconnect US Patent 8154128 3D integrated circuit layer interconnect

Infobox
Patent Number
081541280
Patent Number
81541280
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Infobox
Is a
Patent
Patent
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
0
Patent Number
081541280
Date of Patent
April 10, 2012
0
Patent Application Number
125791920
Date Filed
October 14, 2009
0
Patent Primary Examiner
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Hoai V Pham
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 US Patent 08154128 3D integrated circuit layer interconnect

Infobox
Is a
Patent
Patent
Patent jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent number
08154128
Date of patent
April 10, 2012
Patent application number
12579192
Date Filed
October 14, 2009
Patent primary examiner
‌
Hoai V Pham

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