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US Patent 8154128 3D integrated circuit layer interconnect
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Patent
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Date Filed
October 14, 2009
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Date of Patent
April 10, 2012
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Patent Application Number
12579192
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Patent Citations Received
US Patent 12009386 Structure and method for forming integrated high density MIM capacitor
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US Patent 11715755 Structure and method for forming integrated high density MIM capacitor
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US Patent 11842967 Semiconductor devices with backside power distribution network and frontside through silicon via
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US Patent 11916011 3D virtual ground memory and manufacturing methods for same
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US Patent 11967560 Integrated circuit
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US Patent 11710519 High density memory with reference memory using grouped cells and corresponding operations
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Patent Inventor Names
Hsiang-Lan Lung
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
8154128
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Patent Primary Examiner
Hoai V Pham
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