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US Patent 8314007 Process for fabricating a heterostructure with minimized stress

Patent 8314007 was granted and assigned to Soitec on November, 2012 by the United States Patent and Trademark Office.

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US Patent 12136605 Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics and method for forming the same
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US Patent 12132020 Low temperature bonded structures
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US Patent 12125784 Interconnect structures
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US Patent 12113056 Stacked dies and methods for forming bonded structures
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US Patent 12068278 Processed stacked dies
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US Patent 12027487 Structures for low temperature bonding using nanoparticles
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US Patent 11973056 Methods for low temperature bonding using nanoparticles
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US Patent 11955445 Metal pads over TSV
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US Patent 11955393 Structures for bonding elements including conductive interface features
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US Patent 11948847 Bonded structures
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US Patent 11935907 Image sensor device
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US Patent 11929347 Mixed exposure for large die
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US Patent 11916054 Stacked devices and methods of fabrication
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Edits on 22 Feb, 2024
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edited on 22 Feb, 2024
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US Patent 11908739 Flat metal features for microelectronics applications
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