US Patent 9036482 Bufferless nonblocking networks on chip

Network on Chips (NoC)s with a bufferless and nonblocking architecture are described. Core processors are communicatively coupled together on a substrate with a set of routing nodes based on nonblocking process. A network component routes data packets through the routing nodes and the core processors via communication links. A bufferless cross bar switch facilitates the communication of the data packets and/or path setup packets through the communication links among source processors and destination processors. The communication links include one or more channels, in which a channel comprises a data sub-channel, an acknowledgement sub-channel and a release sub-channel.