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US Patent 9147029 Stretch dummy cell insertion in FinFET process
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Patent
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Date Filed
July 8, 2014
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Date of Patent
September 29, 2015
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Patent Application Number
14325868
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Patent Citations Received
US Patent 11842131 Method and system for generating layout diagram for semiconductor device having engineering change order (ECO) cells
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US Patent 11935833 Method of forming power grid structures
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US Patent 11714947 Method and layout of an integrated circuit
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
9147029
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Patent Primary Examiner
Mohammed Alam
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