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US Patent 9153478 Spacer etching process for integrated circuit design
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Patent
Date Filed
November 15, 2013
Date of Patent
October 6, 2015
Patent Application Number
14081345
Patent Citations Received
US Patent 12125889 Source/drain contact with low-k contact etch stop layer and method of fabricating thereof
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US Patent 12068167 Self-aligned double patterning
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US Patent 12073166 Method and structure for mandrel patterning
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US Patent 12074058 Patterning methods for semiconductor devices
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US Patent 11676821 Self-aligned double patterning
0
US Patent 11699737 Integrated circuit with doped low-k side wall spacers for gate spacers
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US Patent 11749677 Semiconductor structure and methods of forming the same
US Patent 11784056 Self-aligned double patterning
US Patent 11855226 Thin film transistor, semiconductor device and method of fabricating thin film transistor
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US Patent 11894237 Ultra narrow trench patterning with dry plasma etching
0
•••
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
9153478
Patent Primary Examiner
Charles Garber
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