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US Patent 9396999 Wafer level packaging method

Patent 9396999 was granted and assigned to Freescale Semiconductor on July, 2016 by the United States Patent and Trademark Office.

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Current Assignee
Freescale Semiconductor
Freescale Semiconductor
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Date Filed
July 1, 2014
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Date of Patent
July 19, 2016
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Patent Applicant
Freescale Semiconductor
Freescale Semiconductor
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Patent Application Number
14321261
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Patent Citations Received
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US Patent 12125759 Chip integration into cavities of a host wafer using lateral dielectric material bonding
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US Patent 11887934 Package structure and fabrication methods
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US Patent 11927885 Fluoropolymer stamp fabrication method
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US Patent 11931855 Planarization methods for packaging substrates
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US Patent 12087679 Package core assembly and fabrication methods
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US Patent 11705365 Methods of micro-via formation for advanced packaging
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US Patent 11715700 Reconstituted substrate structure and fabrication methods for heterogeneous packaging integration
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US Patent 11837680 Substrate structuring methods
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US Patent 11862546 Package core assembly and fabrication methods
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US Patent 11881447 Package core assembly and fabrication methods
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Patent Inventor Names
Weng F. Yap
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Michael B. Vincent
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
9396999
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Patent Primary Examiner
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Dung Le
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