US Patent 9859335 Semiconductor device having memory cell structure
Patent 9859335 was granted and assigned to United Microelectronics Corporation on January, 2018 by the United States Patent and Trademark Office.
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A semiconductor device includes an interconnection formed above a substrate, and the interconnection comprising interconnect layers respectively buried in dielectric layers; a lower conducting layer formed above the substrate; a memory cell structure formed on the lower conducting layer and buried in one of the dielectric layers; an upper conducting layer formed on the memory cell structure. The memory cell structure includes a bottom electrode formed on and electrically connected to the lower conducting layer; a transitional metal oxide (TMO) layer formed on the bottom electrode; and a top electrode formed on the TMO layer, wherein the upper conducting layer is formed on the top electrode and electrically connected to the top electrode. Also, the lower conducting layer and the upper conducting layer are positioned in the different dielectric layers.
US Patent 09859335 Semiconductor device having memory cell structure US Patent 9859335 Semiconductor device having memory cell structure
US Patent 09859335 Semiconductor device having memory cell structure
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