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Daniel Chang

based in Florida

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Edits on 20 Aug, 2022
"Infobox creation from: https://twitter.com/dchangmiami"
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Golden AI
edited on 20 Aug, 2022
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Location
Miami
Miami
"Edit from table cell"
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godwinno feliks
edited on 20 Aug, 2022
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Twitter URL
https://twitter.com/dchangmiami
Edits on 14 Dec, 2021
"Remove inverse infobox"
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Golden AI
edited on 14 Dec, 2021
Edits made to:
Infobox (-116 properties)
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Patent primary examiner of
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US Patent 7088139 Low power tri-level decoder circuit
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US Patent 7095245 Internal voltage reference for memory interface
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US Patent 7098684 High speed switch
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US Patent 7098690 Programmable I/O element circuit for high speed logic devices
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US Patent 7102385 Dedicated input/output first in/first out module for a field programmable gate array
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US Patent 7109752 Configurable circuits, IC's, and systems
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US Patent 7109753 Programmable logic device with routing channels
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US Patent 7109757 Leakage-tolerant dynamic wide-NOR circuit structure
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US Patent 7109759 Voltage mode current-assisted pre-emphasis driver
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US Patent 7112989 Transmission signal correction circuit
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US Patent 7119577 Method and apparatus for efficient implementation and evaluation of state machines and programmable finite state automata
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US Patent 7119578 Single supply level converter
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US Patent 7126373 Configurable logic circuits with commutative properties
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US Patent 7126376 Logic circuit, timing generation circuit, display device, and portable terminal
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US Patent 7126377 Linear buffer
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US Patent 7129755 High-fanin static multiplexer
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US Patent 7132854 Data path configurable for multiple clocking arrangements
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US Patent 11176706 Systems and methods for automated camera calibration
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US Patent 7138822 Integrated circuit and method of improving signal integrity
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US Patent 7138825 Charge recycling power gate
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US Patent 7142011 Programmable logic device with routing channels
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US Patent 7142014 High frequency XOR with peaked load stage
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US Patent 7142021 Data inversion circuits having a bypass mode of operation and methods of operating the same
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US Patent 7145359 Multiple signal format output buffer
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US Patent 7161387 Semiconductor device and level conversion circuit
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US Patent 7164289 Real time feedback compensation of programmable logic memory
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US Patent 7167024 Methods and circuitry for implementing first-in first-out structure
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US Patent 7173449 Signal transmission system
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US Patent 7176713 Integrated circuits with RAM and ROM fabrication options
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US Patent 7180326 Noise elimination circuit
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US Patent 7183801 Programmable logic auto write-back
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US Patent 7183807 Method, apparatus and system of domino multiplexing
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US Patent 7187197 Transmission line driver
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US Patent 7187202 Circuit for reducing programmable logic pin counts for large scale logic
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US Patent 7187209 Non-inverting domino register
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US Patent 7187211 P-domino output latch
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US Patent 7193445 Non-inverting domino register
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US Patent 7196545 High frequency latch
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US Patent 7199609 Dedicated input/output first in/first out module for a field programmable gate array
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US Patent 7199619 High-speed differential logic multiplexer
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US Patent 7205787 On-chip termination for a high-speed single-ended interface
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US Patent 7205792 Methods and circuitry for implementing first-in first-out structure
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US Patent 7215136 Semiconductor integrated circuits with power reduction mechanism
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US Patent 7215143 Input buffer for multiple differential I/O standards
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US Patent 7215153 Fully differential input buffer with wide signal swing range
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US Patent 7218148 Tracking unity gain for edge rate and timing control
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US Patent 7218153 Word line driver with reduced leakage current
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US Patent 7221189 Dynamic node keeper system and method
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US Patent 7227375 DAC based driver with selectable pre-emphasis signal levels
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US Patent 7227385 Actuation circuit for MEMS structures
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US Patent 7230448 On-DRAM termination resistance control circuit and method thereof
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US Patent 7236007 Methods and systems for achieving improved intellectual property protection for programmable logic devices
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US Patent 7236011 High-speed differential logic buffer
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US Patent 7239169 Semiconductor apparatus capable of preventing occurrence of multiple reflection, driving method, and setting method thereof
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US Patent 7239171 Techniques for providing multiple termination impedance values to pins on an integrated circuit
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US Patent 7242214 Semiconductor integrated circuits with power reduction mechanism
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US Patent 7245151 Logic circuitry powered by partially rectified AC waveform
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US Patent 7248069 Method and apparatus for providing security for debug circuitry
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US Patent 7253657 Apparatus and methods for configuration of programmable logic devices
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US Patent 7253661 Method and apparatus for a configurable latch
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US Patent 7256619 Apparatus to shift to pre-charge mode a dynamic circuit driven by one-shot clock signal during power off mode
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US Patent 7259587 Configurable IC's with configurable logic resources that have asymetric inputs and/or outputs
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US Patent 7259590 Driver for multi-voltage island/core architecture
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US Patent 7259592 Output drivers having adjustable swing widths during test mode operation
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US Patent 7262632 Signal measurement systems and methods
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US Patent 7265578 In-system programming of non-JTAG device using SPI and JTAG interfaces of FPGA device
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US Patent 7268591 Decode structure with parallel rotation
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US Patent 7271614 Buffer circuit with current limiting
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US Patent 7274217 High performance PFET header in hybrid orientation technology for leakage reduction in digital CMOS VLSI designs
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US Patent 7276935 Input buffer with selectable threshold and hysteresis option
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US Patent 7282948 MOS linear region impedance curvature correction
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US Patent 7282951 Reconfigurable processor module comprising hybrid stacked integrated circuit die elements
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US Patent 7285986 High speed, low power CMOS logic gate
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US Patent 7288962 Level shifting multiplexing circuit for connecting a two conductor full duplex bus to a bidirectional single conductor bus
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US Patent 7288965 Semiconductor device and level conversion circuit
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US Patent 7295041 Circuits and methods for detecting and assisting wire transitions
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US Patent 7301370 High-speed differential logic to CMOS translator architecture with low data-dependent jitter and duty cycle distortion
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US Patent 7302513 Programmable crossbar signal processor
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US Patent 7304494 Methods and apparatus to DC couple LVDS driver to CML levels
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US Patent 7304503 Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability
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US Patent 7310006 Semiconductor integrated circuit
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US Patent 7310008 Configurable delay chain with stacked inverter delay elements
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US Patent 7312634 Exclusive-or and/or exclusive-nor circuits including output switches and related methods
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US Patent 7312637 Enhanced timing margin memory interface
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US Patent 7317329 Lookup table circuit
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US Patent 7317334 Voltage translator circuit and semiconductor memory device
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US Patent 7319343 Low power scan design and delay fault testing technique using first level supply gating
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US Patent 7321240 Driver circuit for binary signals
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US Patent 7323900 Semiconductor memory device for adjusting impedance of data output driver
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US Patent 7327166 Reference buffer with improved drift
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US Patent 7330054 Leakage efficient anti-glitch filter
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US Patent 7332931 Leakage efficient anti-glitch filter with variable delay stages
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US Patent 7332937 Dynamic logic with adaptive keeper
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US Patent 7336098 High speed memory modules utilizing on-pin capacitors
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US Patent 7336099 Multiplexer including addition element
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US Patent 7336100 Single supply level converter
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US Patent 7336103 Stacked inverter delay chain
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US Patent 7339402 Differential amplifier with over-voltage protection and method
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US Patent 7342413 Programmable crossbar signal processor with input/output tip interconnection
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US Patent 7342417 Low-leakage level shifter with integrated firewall and method
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US Patent 7342421 CMOS circuit arrangement
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US Patent 7352213 Ac powered logic circuitry
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US Patent 7355437 Latch-up prevention circuitry for integrated circuits with transistor body biasing
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US Patent 7355440 Method of reducing leakage current using sleep transistors in programmable logic device
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US Patent 7355455 Low power consumption MIS semiconductor device
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US Patent 7358767 Efficient multiplexer for programmable chips
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US Patent 7365568 Method and circuit for reducing programmable logic pin counts for large scale logic
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US Patent 7368938 Input termination circuitry with high impedance at power off
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US Patent 7368942 Dedicated resource interconnects
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US Patent 7368945 Logic circuit, timing generation circuit, display device, and portable terminal
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US Patent 7368946 Level-shifting pass gate multiplexer
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US Patent 7368953 Buffer
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US Patent 7375551 Techniques for configuring programmable logic using on-chip nonvolatile memory
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US Patent 7375556 Advanced repeater utilizing signal distribution delay
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US Patent 7385423 Low-power low-voltage buffer with half-latch
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US Patent 7439766 Configurable logic circuits with commutative properties
Edits on 1 Dec, 2021
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Golden AI
edited on 1 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7439766 Configurable logic circuits with commutative properties
Edits on 30 Nov, 2021
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Golden AI
edited on 30 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7385423 Low-power low-voltage buffer with half-latch
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Golden AI
edited on 29 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7375556 Advanced repeater utilizing signal distribution delay
Golden AI profile picture
Golden AI
edited on 29 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7375551 Techniques for configuring programmable logic using on-chip nonvolatile memory
Edits on 26 Nov, 2021
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Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7368953 Buffer
Golden AI profile picture
Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7368945 Logic circuit, timing generation circuit, display device, and portable terminal
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Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7368946 Level-shifting pass gate multiplexer
Golden AI profile picture
Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7368942 Dedicated resource interconnects
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Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7368938 Input termination circuitry with high impedance at power off
Golden AI profile picture
Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7365568 Method and circuit for reducing programmable logic pin counts for large scale logic
Edits on 25 Nov, 2021
Golden AI profile picture
Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7358767 Efficient multiplexer for programmable chips
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Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7355455 Low power consumption MIS semiconductor device
Golden AI profile picture
Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7355440 Method of reducing leakage current using sleep transistors in programmable logic device
Golden AI profile picture
Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7355437 Latch-up prevention circuitry for integrated circuits with transistor body biasing
Golden AI profile picture
Golden AI
edited on 24 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7352213 Ac powered logic circuitry
Edits on 23 Nov, 2021
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Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7342421 CMOS circuit arrangement
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Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7342417 Low-leakage level shifter with integrated firewall and method

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