Is a
Patent attributes
Patent Jurisdiction
Patent Number
Patent Inventor Names
Yeon-Tack Ryu0
Joo-Cheol Han0
Jun-Hwan Yim0
No-Ul Kim0
Bo-Un Yoon0
Ho-Young Kim0
Ja-Eung Koo0
Date of Patent
July 24, 2018
0Patent Application Number
153615160
Date Filed
November 28, 2016
0Patent Citations Received
Patent Primary Examiner
Patent abstract
Disclosed is a method of manufacturing semiconductor devices. A gate trench and an insulation pattern defined by the gate trench are formed on a substrate and the protection pattern is formed on the insulation pattern. A gate dielectric layer, a work function metal layer and a sacrificial layer are sequentially formed the substrate along a surface profile of the gate trench. A sacrificial pattern is formed by a CMP while not exposing the insulation pattern. A residual sacrificial pattern is formed at a lower portion of the gate trench and the gate dielectric layer and the work function metal layer is etched into a gate dielectric pattern and a work function metal pattern using the residual sacrificial pattern as an etch stop layer.
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