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US Patent 10707087 Processing stacked substrates
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Patent
Date Filed
December 19, 2017
Date of Patent
July 7, 2020
Patent Application Number
15846731
Patent Citations
US Patent 10157766 Method of fabricating a semiconductor device
Patent Citations Received
US Patent 11552041 Chemical mechanical polishing for hybrid bonding
US Patent 12136605 Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics and method for forming the same
0
US Patent 11476213 Bonded structures without intervening adhesive
US Patent 11515202 3D IC method and device
US Patent 11515279 Low temperature bonded structures
US Patent 11538781 Integrated device packages including bonded structures
US Patent 12125784 Interconnect structures
0
US Patent 12132020 Low temperature bonded structures
0
US Patent 11462419 Microelectronic assemblies
US Patent 11600542 Cavity packages
•••
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
10707087
Patent Primary Examiner
Bilkis Jahan
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