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US Patent 10985133 Die processing

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
June 24, 2020
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Date of Patent
April 20, 2021
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Patent Application Number
16910432
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Patent Citations
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US Patent 10276619 Semiconductor device structure with a conductive feature passing through a passivation layer
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US Patent 10269756 Die processing
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US Patent 10714449 Die processing
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US Patent 10026605 Method of reducing residual contamination in singulated semiconductor die
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US Patent 10075657 Edgeless large area camera system
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Patent Citations Received
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US Patent 12136605 Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics and method for forming the same
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US Patent 12113054 Non-volatile dynamic random access memory
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US Patent 12113056 Stacked dies and methods for forming bonded structures
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US Patent 12125784 Interconnect structures
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US Patent 12132020 Low temperature bonded structures
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US Patent 11621246 Diffused bitline replacement in stacked wafer memory
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US Patent 11626363 Bonded structures with integrated passive component
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US Patent 11631586 Heterogeneous annealing method
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US Patent 11631647 Integrated device packages with integrated device die and dummy element
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US Patent 11652083 Processed stacked dies
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•••
Patent Inventor Names
Cyprian Emeka Uzoh
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
10985133
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Patent Primary Examiner
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Anthony Ho
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