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US Patent 11056390 Structures and methods for reliable packages
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Patent
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Date Filed
December 18, 2019
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Date of Patent
July 6, 2021
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Patent Application Number
16718820
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Patent Citations
US Patent 10446456 Integrated circuits protected by substrates with cavities, and methods of manufacture
US Patent 10008844 Cable seal
US Patent 10026605 Method of reducing residual contamination in singulated semiconductor die
US Patent 10075657 Edgeless large area camera system
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US Patent 10269756 Die processing
US Patent 10204893 Stacked dies and methods for forming bonded structures
US Patent 10276619 Semiconductor device structure with a conductive feature passing through a passivation layer
US Patent 10276909 Structure comprising at least a first element bonded to a carrier having a closed metallic channel waveguide formed therein
US Patent 10727219 Techniques for processing devices
Patent Citations Received
US Patent 12113056 Stacked dies and methods for forming bonded structures
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US Patent 11476213 Bonded structures without intervening adhesive
US Patent 11538781 Integrated device packages including bonded structures
US Patent 11955463 Direct bonded stack structures for increased reliability and improved yield in microelectronics
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US Patent 11967575 Bond enhancement structure in microelectronics for trapping contaminants during direct-bonding processes
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US Patent 12068278 Processed stacked dies
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US Patent 12080672 Direct gang bonding methods including directly bonding first element to second element to form bonded structure without adhesive
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US Patent 11462419 Microelectronic assemblies
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US Patent 11631647 Integrated device packages with integrated device die and dummy element
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US Patent 11652083 Processed stacked dies
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•••
Patent Inventor Names
Liang Wang
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Cyprian Emeka Uzoh
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Guilian Gao
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Hong Shen
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Arkalgud R. Sitaram
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11056390
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Patent Primary Examiner
Sheikh Maruf
0
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