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US Patent 11295822 Multi-state programming of memory cells

Patent 11295822 was granted and assigned to Micron Technology on April, 2022 by the United States Patent and Trademark Office.

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Is a
Patent
Patent

Patent attributes

Patent Applicant
Micron Technology
Micron Technology
Current Assignee
Micron Technology
Micron Technology
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11295822
Date of Patent
April 5, 2022
Patent Application Number
16993831
Date Filed
August 14, 2020
Patent Citations
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US Patent 10163506 Apparatuses including memory cells and methods of operation of same
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US Patent 10546632 Multi-level self-selecting memory device
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US Patent 10102891 Double-polarity memory read
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US Patent 10381075 Techniques to access a self-selecting memory device
Patent Citations Received
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US Patent 11514983 Identify the programming mode of memory cells based on cell statistics obtained during reading of the memory cells
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US Patent 11664073 Adaptively programming memory cells in different modes to optimize performance
0
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US Patent 11664074 Programming intermediate state to store data in self-selecting memory cells
0
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US Patent 11694747 Self-selecting memory cells configured to store more than one bit per memory cell
0
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US Patent 11783902 Multi-state programming of memory cells
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US Patent 11880571 Counter-based methods and systems for accessing memory cells
0
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US Patent 11984191 Pulse based multi-level cell programming
0
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US Patent 12080359 Identify the programming mode of memory cells during reading of the memory cells
0
...
Patent Primary Examiner
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Son T. Dinh
CPC Code
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G11C 16/12
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G11C 16/0483
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G11C 16/3454
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G11C 11/5628
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G11C 16/10

The present disclosure includes apparatuses, methods, and systems for multi-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of four possible data states by applying a first voltage pulse to the memory cell wherein the first voltage pulse has a first polarity and a first magnitude, and applying a second voltage pulse to the memory cell wherein the second voltage pulse has a second polarity and a second magnitude, and the second voltage pulse is applied for a shorter duration than the first voltage pulse.

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