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US Patent 11380597 Bonded structures
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Patent
0
Date Filed
June 18, 2018
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Date of Patent
July 5, 2022
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Patent Application Number
16011525
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Patent Citations
US Patent 10026605 Method of reducing residual contamination in singulated semiconductor die
US Patent 10002844 Bonded structures
US Patent 10075657 Edgeless large area camera system
0
US Patent 10204893 Stacked dies and methods for forming bonded structures
US Patent 10269756 Die processing
US Patent 10276619 Semiconductor device structure with a conductive feature passing through a passivation layer
US Patent 10276909 Structure comprising at least a first element bonded to a carrier having a closed metallic channel waveguide formed therein
US Patent 10446456 Integrated circuits protected by substrates with cavities, and methods of manufacture
US Patent 10446487 Interface structures and methods for forming same
US Patent 10446532 Systems and methods for efficient transfer of semiconductor elements
•••
Patent Citations Received
US Patent 11978724 Diffused bitline replacement in memory
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US Patent 12068278 Processed stacked dies
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US Patent 12074092 Hard IP blocks with physically bidirectional passageways
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US Patent 12113054 Non-volatile dynamic random access memory
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US Patent 12113056 Stacked dies and methods for forming bonded structures
0
US Patent 11694925 Diffusion barrier collar for interconnects
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US Patent 11881454 Stacked IC structure with orthogonal interconnect layers
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US Patent 11621246 Diffused bitline replacement in stacked wafer memory
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US Patent 11894345 Integrated voltage regulator and passive components
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US Patent 11916054 Stacked devices and methods of fabrication
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•••
Patent Inventor Names
Liang Wang
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Rajesh Katkar
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11380597
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Patent Primary Examiner
Jaehwan Oh
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CPC Code
H01L 23/26
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H01L 24/05
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H01L 27/085
0
H01L 23/10
0
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